1. Field of the Invention
The present invention relates to the field of multi-media computer systems. More specifically, the present invention relates to a method and circuitry for processing sync pulses in a multi-media PC wherein the circuitry automatically synchronizes the polarity of the horizontal and vertical sync pulses respectively.
2. Description of Related Art
Personal computer (PCs) systems have evolved into multi-media systems adapted to run multi-media software including video information displayed on PC monitors and other video display monitors. The introduction of multi-media computers also means that computer users may now purchase off the shelf add-on peripherals such as graphics and video cards to give their PCs multi-media capabilities.
As the use of multi-media systems has increased in popularity, so has the need to process multi-media information. To adequately handle the increased popularity of multi-media information processing, system designers must consider new techniques of controlling the simultaneous processing and displaying of video and graphics data in a multi-media system without losing display clarity, picture distinction, or over-task system resources. The need to design new video processing and display techniques may also be complicated by the need to simplify the use of such technology for less sophisticated users.
FIG. 1 is a simplified block diagram of a multi-media computer system 100. System 100 includes a central processing unit (CPU) 110 for processing information, main memory 120 coupled to CPU 110 for storing data and instructions needed by CPU 110, system bus 105 coupled to CPU 110 for communicating information between CPU 110 and other peripheral devices in system 100. System 100 also includes video graphics adapter (VGA) controller 130 which couples to system bus 105 for processing video and graphics data in system 100, display monitor 140 including a display screen to display video and graphics data in system 100. System 100 further includes video card 150 for generating video data in system 100.
In the system shown in FIG. 1, when graphics and video data are displayed on display monitor 140, VGA controller 130 includes internal registers which store video and graphics data which may be used for display hardware control (i.e., display monitor 140). VGA controller 130 controls graphics information displayed in display monitor 140. The information controlled by VGA controller 130 may include horizontal and vertical synchronization pulses (VSYNC.+-.304 and HSYNC) and other video signals.
Horizontal and vertical sync signals dictate the scan rate of display in display monitor 140. The horizontal sync signal occurs once every horizontal line on the screen in display monitor 140; thereby synchronizing display monitor 140 to video card 150. Video card 150 sends data to display monitor 140 via a serial video bus. The serial video data stream feeding display monitor 140 from video card 150 begins at the left hand side of the screen of display monitor 140 and scans across to the right hand side of the screen. At the end of a line, a horizontal sync signal is asserted by the VGA controller 130 to indicate the end of a scan line.
After receiving the horizontal pulse, display monitor 140 sends an electronic beam back to the left border of the screen and begins scanning to the right. In order to synchronize display data, the display monitor 140 and VGA controller 130 have to be compatible. Compatibility is required because if VGA controller 130 is sending data too slowly, the screen scanning mechanism in display monitor 140 will reach the right hand side of the screen and then wait for the next horizontal sync pulse. Waiting for the next HSYNC pulse may result in the left portion of the video or graphics data being displayed without the right portion of the display. Furthermore, if the sync pulses are sent out too quickly, the screen scanning mechanism will never refresh the right portion of the screen resulting in display distortions in display monitor 140.
To prevent display distortions in display monitor 140, VGA controller 130 includes internal registers which store data which may be used to program the HSYNC and VSYNC signal as well as a field storing data indicative of the polarity of the pulses. The polarity data controls the pulse shape of the horizontal and vertical sync pulses which in turn control the vertical and horizontal sizes of the screen. The polarity of the sync pulses also alerts the screen as to how many vertical and horizontal lines should be displayed. HSYNC and VSYNC signals must possess a correct polarity corresponding to the display monitor 140. Otherwise, a reverse or negative image may be produced on the screen on display monitor 140.
Many prior art graphics and video cards are auto-synchronizing which means that the display screens in display monitor 140 must be capable of achieving vertical and horizontal synchronization. To achieve such synchronization, the display monitor 140 must also be capable of detecting the polarity of the horizontal and vertical sync pulses. After detecting the polarity of the sync pulses, display monitor 140 must be able to synchronize the polarity of the sync pulses in order to increase the number of vertical and horizontal lines that can be displayed.
To synchronize the polarity of the sync pulses, many prior art systems use computer program software stored in registers in the video card and VGA controller 130 to program the polarity of the sync signals. VGA controller 130 and video card 150 are therefore charged with synchronizing the polarity of the sync pulses by communicating with their respective registers over the system bus 105 when a program detects that display mode in display monitor 140 has changed or is about to change.
Using software to control polarity synchronization thus requires the VGA controller 130 to contend with other peripheral devices in system 100 to communicate with CPU 110. Such bus contention can be expensive and time consuming since VGA controller 130 may not always have priority over other system devices. The VGA controller 130 may then have to wait to gain control of the system bus 105 if it loses priority to other system devices. Such wait periods may result in display distortions, delay in displaying graphics and video data, etc.
Another problem with using software to perform polarity synchronization of sync pulses is the cost associated with upgradability. Anytime CPU 110 or VGA controller 130 is upgraded, the polarity synchronization software must also be upgraded to insure compatibility. Such software upgrades can be expensive and may lag behind hardware upgrades which may often result in the ability to switch the video card 150 and VGA controller 130 among different computer systems.
Yet another problem with the prior art system may be that the user of a software programmable graphics controller and video card, will have to know anytime the display mode changes, for example from 1024.times.768 pixels to 1280.times.1024 pixels, in the computer system in order to reprogram the graphics controller and the video card. This can often be a difficult task, especially if the user is not sophisticated enough or does not know how to program the different cards.
To solve the problem associated with using software to synchronize the polarity of sync pulses take to synchronize display signals, an improved and less expensive way of achieving sync signals polarity synchronization in a graphics controller and video card is desired.